FIG. 1 illustrates a block diagram of a sigma-delta analogue/digital converter (SD-ADC). The latter comprises a feedback control loop comprising a loop filter 1, a quantizer 2 and a digital/analogue converter 3 (DAC). An analogue signal X is applied to the input of the SD-ADC. The difference between the analogue input signal X and the output signal of the DAC 3 is fed to the analogue loop filter 1 whose output drives the quantizer 2. The output of the quantizer 2 generates an oversampled digital signal Y whose mean value corresponds to the analogue input signal X. The SD-ADC illustrated in FIG. 1 is a multilevel SD-ADC (also called a multibit SD-ADC). In a multilevel SD-ADC, the quantizer 2 has a plurality N of quantization thresholds. If no code conversion is carried out in the quantizer, the output signal Y of the quantizer 2 is a signal having a width of N bits (where N>1), this signal being present in thermometer code. The output signal Y of the quantizer 2 is converted, using the DAC 3, into an analogue signal which is compared with the analogue input signal X. In the steady state of the control loop, the analogue input signal X and the output signal of the DAC 3 correspond to one another.
A code converter (not illustrated) which converts the output signal of the quantizer from the thermometer code representation into the binary code representation is typically connected downstream of the loop illustrated in FIG. 1. In addition, a digital low-pass filter and a decimator (not illustrated) are arranged on the output side of the code converter, the low-pass filter forming a mean value and the decimator reducing the sampling rate.
The effective resolution of the multilevel SD-ADC is decisively determined by the linearity of the internal DAC 3. The DAC 3 generally comprises N standard cells which are activated or deactivated as a function of the thermometer code output signal (which has a width of N bits) of the quantizer. The standard cells are typically switchable standard current sources, the output signal of the DAC 3 resulting from the superimposition of the currents of the N standard current sources. Ideally, the standard cells of the DAC 3 are completely identical. However, in the case of a real DAC, the standard cells differ slightly, i.e. the output currents of the standard current sources are not completely identical in the activated state. A so-called “mismatch” thus occurs. This gives rise to non-linear distortion of the output signal of the DAC 3. In the case of discrete frequencies (“spurious frequencies”), this results in interference components, which can generally no longer be filtered out, in the spectrum of the output signal of the SD-ADC.
In order to increase the linearity of the DAC 3, it is known practice to provide a so-called DEM block (DEM—dynamic element matching; frequently also referred to as a randomizer or scrambler block) on the input side of the DAC 3, said block dynamically scrambling the thermometer code of the output signal of the quantizer 2, i.e. swapping the digits of the code signal. In this case, a code signal “0011100” is generated, for example, from a thermometer code “1110000” having a width of 7 bits. For a particular output signal of the quantizer 2, it is thus not always the same standard cells but rather different standard cells of the DAC 3 which are activated at different times, the number of active standard cells remaining constant. The linearity error is reduced in this manner.
FIG. 2 illustrates a block diagram of a multilevel SD-ADC having an additional DEM block 4 for code scrambling. Signals and circuit components which are provided with the same reference symbols in FIG. 1 and FIG. 2 correspond to one another. The ADC illustrated in FIG. 2 has N=7 quantization thresholds which correspond to the seven references REF0–REF6, where REFi<REFi+1. Each of the references REFi is assigned to a comparator 5.i which receives the corresponding reference REFi via the inverted input. The references are typically voltage references which are derived from the node voltages of a resistor string. However, current references may also be used instead of voltage references.
The output signal Qi (which has been sampled using an additional D-type flip-flop 6.i) of each comparator 5.i has a logic 1 if the input signal of the quantizer is greater than the corresponding reference REFi. Otherwise, the signal Qi corresponds to a logic 0. If the input signal of the quantizer is in the range of greater than REFj and less than REFj+1, all of the comparators 5.1 to 5.j provide a logic 1 at their output, while the comparators 5.j+1 to 5.N−1 generate a logic 0 at their output. The resultant code of the output signal Y (which has a width of N=7 bits and results from the combination of the binary signals Qi) of the quantizer is referred to as “thermometer code” because of the analogy to a liquid thermometer.
The output signal Y of the quantizer 2 is received by the DEM block 4, the individual digits of the signal Y being scrambled in the DEM block, as already explained above. In order to carry out code scrambling, the DEM block 4 comprises a digital logic unit which has a delay time or latency, i.e. the output signal of the DEM block 4 only reacts to a change in the signal Y with a certain delay. In the control loop, this latency acts as dead time and impairs the stability properties of the control loop.
The document U.S. Pat. No. 6,346,898 B1 discloses that impairment of the stability of the control loop, which is associated with code scrambling, can be circumvented if—instead of a DEM block 4 between the output of the quantizer 2 and the input of the DAC 3—a DEM block 4′ is placed upstream of the inverting inputs of the quantizer 2. The resultant SD-ADC is illustrated in FIG. 3, signals and circuit components which are provided with the same reference symbols in FIG. 2 and FIG. 3 corresponding to one another. In the SD-ADC illustrated in FIG. 3, the DEM block 4′ is used to dynamically scramble the assignment of the references REFi to the comparators 5.i. This means that, for a particular input signal of the quantizer 2, different bits Qi of the signal Y and thus, as in FIG. 3, also different standard cells of the DAC 3 are activated at different times. The effect of the DEM block 4′ which is outside the control loop in FIG. 3 is thus analogous to that of the DEM block 4 from FIG. 2 which is arranged inside the control loop, although the DEM block 4′ illustrated in FIG. 3 is not associated with any additional dead time inside the control loop. In contrast to the DEM block 4 illustrated in FIG. 2, the DEM block 4′ illustrated in FIG. 3 thus does not reduce the stability of the control loop.
FIG. 4 indicates an implementation example of the DEM block 4′ illustrated in FIG. 3. Signals and circuit components which are provided with the same reference symbols in FIG. 4 and FIG. 3 correspond to one another. In this case, it should be taken into account that, for reasons of a simplified illustration, only the scrambling of 4 of the total of 7 references REFi is illustrated. The DEM block 4′ comprises a switching network 7 which can be used to assign each individual reference REFi to each comparator 5.i. The switching network 7 is controlled using a control apparatus 8, the control apparatus 8 providing a digital control signal 9 for controlling the dynamic assignment between the references REFi and the comparators 5.i via the switching network 7. In this case, the digital control signal 9 is obtained in the control apparatus 8 as a function of the output signal Y of the quantizer 2. The control apparatus 8 generates a control signal 9 such that, on average, all of the bits Qi have a logic 1 equally often, with the result that all of the standard cells of the DAC 3 are used equally often.
As regards the implementation of the control apparatus, the document U.S. Pat. No. 6,346,898 B1 cited above indicates a very complicated implementation example which comprises a multiplicity of individual circuit blocks (cf. FIG. 3 and column 3, lines 61 and 62, of the document U.S. Pat. No. 6,346,898 B1). In this case, the complicated implementation of the control apparatus 8 is based on the idea of selecting, from the total number of N standard cells of the DAC 3, precisely those m standard cells (where m depends on the input signal of the quantizer 2 at the time k) which have the greatest need for activation at any time k (cf. column 2, lines 23 to 31, in the document U.S. Pat. No. 6,346,898 B1). The need for activation of a standard cell of the DAC 3 depends on the previous overall use of the respective standard cell of the DAC 3, that standard cell which was previously used least having the greatest need for activation.